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Portrait of Jae-Yoon Kim

Alumni · B.S. · 2023

Jae-Yoon Kim

Digital VLSI · CTLE · DLL

LG Electronics

Status

B.S. · 2023

Alumni cohort

2023

Research projects

Digital VLSI (place and route)

Continuous-time linear equalizer (CTLE) design

Capstone design: delay-locked loop (DLL)

Affiliation

LG Electronics · LG Digital Park, Pyeongtaek

Research

Digital VLSI · CTLE · DLL

CV not available

Research achievements

0 journal articles · 1 conference paper

Publications listed in the AD-Lab archive. Entries are ordered from newest to oldest within each category.

Conference papers

2022

IEIE Fall Annual Conference, Gonjiam, November 2022 · Capstone project

Domestic conference

Study on Jitter Analysis and Reduction Methods in DLL

J.-W. Hyun, J.-Y. Kim, S.-J. Kim, J.-W. Nam (corresponding author)

Bold blue names* indicate corresponding authors. Funding and awards are included where recorded in the source.