Principal investigator
Jaewon Nam
Analog and mixed-signal IC design · Cryogenic CMOS · Hardware security · Design automation
Department of Electronic Engineering · SeoulTech
- Position
Associate Professor, Seoul National University of Science and Technology
- Adjunct appointment
Adjunct Professor · Department of Quantum Convergence Physics · SeoulTech (department scheduled to open in 2027)
- Visiting
Visiting Scholar, IMEC, Belgium · September 2026–August 2027
- Phone
+82-2-970-6478
- Office
Changhak Hall, Room 233
Research interests
- Analog and mixed-signal integrated circuit design, including analog, RF, and digital CAD
- Machine learning and mixed-signal accelerators
- Cryogenic CMOS electronics, including analog-to-digital and digital-to-analog converters
- Hardware security, physically unclonable functions (PUFs), and side-channel attack protection
Education
- 2019
Ph.D. in Electrical Engineering
University of Southern California, USA · Electrophysics
Thesis: Energy-efficient design techniques and architectures for high-speed (GS/s) analog-to-digital converters
Advisor: Mike Shuo-Wei Chen, IEEE Fellow
- 2018
M.S. in Electrical Engineering
University of Southern California, USA · Electrophysics
- 2008
M.S. in Electrical Communication Engineering
Korea Advanced Institute of Science and Technology (KAIST)
Thesis: Systematic power optimizing cyclic ADC design
Advisor: Sang-Gug Lee
- 2006
B.S. in Electrical Communication Engineering
Korea Advanced Institute of Science and Technology (KAIST)
Graduated with honors
- 2001–2003
Kyungbuk Science High School
March 2001–February 2003
Professional experience
- Oct 2026–present
Associate Professor · SeoulTech
Department of Electronic Engineering
- Sep 2026–Aug 2027
Visiting Scholar · IMEC
Belgium
- Sep 2020–Sep 2026
Assistant Professor · SeoulTech
Department of Electronic Engineering
- 2019–2020
Analog Engineer · Intel Corporation
Oregon, USA
- 2017
Graduate Intern · Intel Corporation
California, USA
- 2008–2012
Research Staff · ETRI
Electronics and Telecommunications Research Institute, South Korea
- 2006–2007
Graduate Intern · ETRI
Electronics and Telecommunications Research Institute, South Korea
Professional service
- 2023–present
Technical Program Committee Member · IEEE ISOCC
International SoC Design Conference · Data Converters
Honors and awards
- 2020
Online-Lecture Contest Recognition
SeoulTech
- 2019
Outstanding Student Paper Award (3rd place)
IEEE Custom Integrated Circuits Conference (CICC)
- 2012
Ph.D. Fellowship
USC Viterbi School of Engineering
- 2009
President Award
ETRI
- 2006
President Award
KAIST
Invited talks
- Sep 2021
GS/s ADC design trends for high-speed links
RF/Analog Workshop · Host: Jae-Duk Han
- Feb 2021
ADC-based wireline receiver design
CNBU · Host: Jong-Phil Hong
- Dec 2020
ADC-based wireline receiver
ISE · Host: Seung-eun Lee
- Oct 2020
25 Gbps high-speed PAM4 wireline transceiver
ETRI · Host: Ja-Yol Lee
- Jun 2019
ADC-based wireline receiver
Intel Corporation · Host: Frank O’Mahony
- May 2019
Low-power ADC design techniques
Lawrence Berkeley National Laboratory · Host: Carl Grace
- Feb 2019
Advanced high-speed ADC
University of Washington Bothell · Host: Seungkeun Choi
- Jan 2019
Advanced high-speed ADC
Georgia Tech · Host: Hua Wang
- Oct 2018
ADC-based wireline receiver
Marvell Semiconductor · Host: Manisha Gambhir
- Aug 2013
Embedded passive-gain SAR ADC
Qualcomm Atheros · Host: David Su