AD Lab — Advanced Integrated Circuit Design Lab, SeoulTech
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RESEARCH · HARDWARE SECURITY

Hardware security.
Rooted in silicon.

Silicon identity, on-chip threat sensing, and circuit verification for secure systems on chip.

01 / HARDWARE FOUNDATIONS

Security begins inside the chip

Connected devices need a trusted physical foundation as well as secure software and communication protocols. Probing, abnormal operating conditions, and power or electromagnetic leakage can expose weaknesses at the integrated-circuit level. Our research brings device identity, threat detection, and protective circuit operation into the chip, developing hardware foundations for zero-trust systems.

A system-level approach connects the PUF core with low-power sensing, response logic, error correction, and built-in self-test (BIST). Circuit protection and external evaluation work together: one provides on-chip controls, while the other tests reliability and the defined attack scenarios.

Security system with attack detection, low-power sensors, power-pattern analysis, silicon PUF, error correction, encoding, and built-in self-test, followed by off-chip evaluation.
Chip-level security architectureAdapted from AD-Lab presentation material, slide 6. Original diagram composition and colors are retained with English labels. Select the image to enlarge.

02 / DEVICE FINGERPRINTING

Silicon PUFs: a reproducible chip identity

A physically unclonable function (PUF) uses manufacturing variation to produce device-specific responses. In an SRAM PUF, small mismatches between circuit elements influence the resolved bit values. A challenge selects an evaluation condition, and the corresponding response can support device authentication or key reconstruction within a suitable protocol.

The design goal is a response that is repeatable on the same chip and sufficiently different across chips. This can reduce reliance on permanently stored secret keys, while reliability processing and secure protocol design remain essential. PUFs provide reproducible identity; true random number generators (TRNGs) provide fresh entropy.

Stored-key architecture with an MCU, cryptographic engine, nonvolatile key storage, and server challenge-response exchange.PUF architecture where manufacturing variation contributes to a chip-specific response, with protocol logic and a server challenge-response exchange.
From stored secrets to a silicon identityAdapted from AD-Lab presentation material, slide 7. Original panel colors and circuit connections are retained; labels are adapted for technical accuracy. Select either panel to enlarge.
Design targetCircuit and evaluation focus
Reliable responsesControl bit-error rate and the fraction of unreliable bits over supply-voltage, temperature, and noise variations; use stable-bit selection or error correction when needed.
Efficient memory-based PUFsExplore SRAM-based structures and the reuse of memory resources while maintaining a clear boundary between normal computation and authentication.
Resistance to modelingEvaluate whether responses to unseen challenges can be predicted from collected challenge-response pairs (CRPs).

03 / SENSE · SUPPRESS · RESPOND

Sensor-assisted security SoC

A PUF core benefits from protection around its physical operating environment. The research architecture combines temperature, light, and electromagnetic sensing with supply conditioning and countermeasure control. Sensors indicate abnormal conditions; protective circuits seek to reduce information leakage and coordinate the response with PUF operation.

Temperature, light, and electromagnetic sensors connected to a PUF core, secure LDO, and countermeasure-operation block with a feedback path.
Sensor-assisted PUF protectionAdapted from AD-Lab presentation material, slide 8. This is a research architecture connecting sensing, leakage reduction, and countermeasure control. Select the image to enlarge.
FunctionResearch objective
SenseDetect relevant environmental or physical changes with low-power on-chip sensors.
SuppressReduce correlations between sensitive circuit activity and observable power or electromagnetic signals.
RespondCoordinate the sensor decision and protective operation within the security SoC.

Sensor thresholds, response latency, false alarms, and normal-operation power must be evaluated together. Our CMOS light-detection work provides a published sensing building block, while PUF BIST and decoy-data studies connect sensing and response to system-level validation.

04 / DEFINED THREATS, MEASURABLE BEHAVIOR

Verification across the threat model

We define feasible attack scenarios and test the relevant circuit response. The scope includes physical probing, fault injection, abnormal temperature conditions, and power or electromagnetic side-channel observations. The assessment links security behavior with the reliability and resource cost of the protected system.

  • PUF characterization: repeatability, uniqueness, response-bit balance, and reliability across operating conditions.
  • BIST and reliability: repeatable on-chip evaluation of SRAM PUF responses and unstable bits.
  • Attack detection: sensor sensitivity, detection latency, and behavior at the boundary between normal and abnormal operation.
  • Security evaluation: modeling resistance and information leakage under the defined threat scenarios.

05 / RELATED AD-LAB PUBLICATIONS

From circuit building blocks to security systems

The following studies connect SRAM PUF design, entropy generation, attack sensing, and reliability verification.

Reliable silicon identity · 2024

A Reconfigurable SRAM CRP PUF with High Reliability and Randomness (opens in a new tab)

Van Khanh Pham, Chi Trung Ngo, Jae-Won Nam, Jong-Phil Hong (corresponding author)

Electronics (vol. 13 (2), no. 309, pp. 1-13)

Timing control and symmetric layout reduce response bias in a reconfigurable SRAM challenge-response PUF. This work connects device variation with reliable, device-specific authentication.

Funding NRF-2020R1A6A1A12047945, NRF-2021R1A2C2005258

Publication details

On-chip light detection · 2023

High-speed Light Detection Sensor for Hardware Security in Standard CMOS Technology (opens in a new tab)

Dana Kim, Jong-Phil Hong, Jiwon Lee, Jae-Won Nam (corresponding author)

IEEE Transactions on Circuits and Systems II: Express-Briefs · (vol. 70, no. 10, pp. 3917-3921) · ISICAS-2023 Special Issue

Finger- and well-type photodiodes and initialization logic improve light detection in standard CMOS. The sensor provides a circuit building block for detecting optical exposure of a protected chip.

Funding NRF-2021R1A2C2005258, IITP-2023-RS-2022-00156295

Publication details

Related conference contributions

Bold blue names* indicate corresponding authors.

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