RESEARCH POSTERS

Research, on display.

Circuit architectures, silicon measurements, and research results. Select a poster to explore it in detail.

Research poster: Light-Sensor-Based Countermeasure against Physical Attacks in SRAM PUF

2025 · ISOCC · Chip Design Contest

Light-Sensor-Based Countermeasure against Physical Attacks in SRAM PUF

Research poster: MASH Digital Delta-Sigma Modulators for the CMOS Qubit Controller

2025 · IEEE ISVLSI

MASH Digital Delta-Sigma Modulators for the CMOS Qubit Controller

Research poster: Adjustable Majority Voting Algorithm for Stability Improvement in SRAM-Based CMOS PUFs

2025 · IDEC Congress · Chip Design Contest

Adjustable Majority Voting Algorithm for Stability Improvement in SRAM-Based CMOS PUFs

Outstanding Poster Award

Research poster: Quantitative Performance Comparison of WebGL-Based 3D Frameworks Under Identical Experimental Conditions

2025 · IEIE Summer Annual Conference

Quantitative Performance Comparison of WebGL-Based 3D Frameworks Under Identical Experimental Conditions

Research poster: Design of Pulse Shaping Module for Multiple Qubit Control Pulse Generation

2025 · IEIE Summer Annual Conference

Design of Pulse Shaping Module for Multiple Qubit Control Pulse Generation

Research poster: Implementation of a Second-Order Delta-Sigma ADC and Digital Filter Using Switched-Capacitor Integrator

2025 · IEIE Summer Annual Conference

Implementation of a Second-Order Delta-Sigma ADC and Digital Filter Using Switched-Capacitor Integrator

Research poster: Measurement-Driven Standard CMOS Photodiode Modeling and Layout Automation

2025 · IEIE Summer Annual Conference

Measurement-Driven Standard CMOS Photodiode Modeling and Layout Automation

Research poster: Cryogenic Current Bias Technique Employing ZTC Point

2025 · IEIE Summer Annual Conference

Cryogenic Current Bias Technique Employing ZTC Point

Research poster: Improved Built-in Self-Test Architecture for SRAM-Based PUF Reliability Evaluation

2025 · IEIE Summer Annual Conference

Improved Built-in Self-Test Architecture for SRAM-Based PUF Reliability Evaluation

Research poster: ML-Based Design Optimization for Dickson Charge Pump

2025 · 7th ISE Winter Conference

ML-Based Design Optimization for Dickson Charge Pump

Research poster: Analysis of ROM-Based DDFS Architecture Employing Quarter Method

2023 · IEEE ICEIC

Analysis of ROM-Based DDFS Architecture Employing Quarter Method

Research poster: Regression Model-Based VCO Design Optimization Technique

2023 · IEEE ICEIC

Regression Model-Based VCO Design Optimization Technique

Research poster: Machine Learning Based EV Charger Location Optimization

2023 · IEIE Summer Annual Conference

Machine Learning Based EV Charger Location Optimization

Outstanding Student Paper Award

Research poster: Study on Direct Digital Frequency Synthesis

2022 · RF & Analog Workshop

Study on Direct Digital Frequency Synthesis

Research poster: Analysis on Efficiency of DC-DC Converter through Power-Loss Modeling

2022 · SeoulTech Electronic Engineering Capstone Exhibition

Analysis on Efficiency of DC-DC Converter through Power-Loss Modeling

Dean’s Award · College of Information and Communication Engineering

Research poster: Study on Jitter Analysis and Reduction Methods in DLL

2022 · IEIE Conference

Study on Jitter Analysis and Reduction Methods in DLL

Research poster: Loss Analysis and Modeling of Asynchronous Buck Converter

2022 · IEIE Summer Annual Conference

Loss Analysis and Modeling of Asynchronous Buck Converter

Research poster: Study on Discard Rate of SRAM-Based PUF

2022 · IEIE Summer Annual Conference

Study on Discard Rate of SRAM-Based PUF

Research poster: Implementation of a Low-Cost Linear CMOS Temperature Sensor for Biomedical Application

2022 · IEIE Summer Annual Conference

Implementation of a Low-Cost Linear CMOS Temperature Sensor for Biomedical Application

Research poster: A 12.8-Gbaud ADC-Based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter in 65nm CMOS

2019 · IEEE CICC

A 12.8-Gbaud ADC-Based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter in 65nm CMOS

Best Student Paper Award

Research poster: A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation

2018 · IEEE VLSI

A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation

Research poster: A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm CMOS

2013 · IEEE CICC

A 95-MS/s 11-bit 1.36-mW Asynchronous SAR ADC with Embedded Passive Gain in 65nm CMOS

Poster images retain their original language and resolution. Event details and awards follow the lab’s poster archive.